A delta-sigma type analog/digital converter (delta-sigma A/D converter) is an A/D converter based on an oversampling technique, and is used for digitizing a relatively low speed signal, such as an audio signal and a sensor signal. The delta-sigma A/D converter has an excellent monotonously increasing characteristic, and can attain high resolution, such as 16 bits, by a comparatively simple circuit. The delta-sigma A/D converter is used, for example, as an A/D converter incorporated in a micro controller unit (MCU).
The delta-sigma A/D converter includes a delta-sigma modulator which performs delta-sigma modulation of an input analog signal, and a decimation filter which generates an A/D conversion result from the delta-sigma modulated signal. FIG. 6 is a view illustrating a configuration example of a delta-sigma A/D converter including a 1-bit delta-sigma modulator. In FIG. 6, reference character MOD denotes the delta-sigma modulator, and reference character FLT denotes the decimation filter. The delta-sigma modulator MOD delta-sigma modulates an input analog signal Vin at a frequency (oversampling frequency) of several ten to several hundred times the signal frequency of the input analog signal Vin, and outputs a 1-bit delta-sigma modulated signal D1. The 1-bit delta-sigma modulated signal D1 is a pulse density modulated signal. When the input analog signal Vin is large, the number of bits “1” included in the pulse density modulated signal is increased, and when the input analog signal Vin is small, the number of bits “0” included in the pulse density modulated signal is increased. The decimation filter FLT extracts signal band components from the 1-bit delta-sigma modulated signal D1 generated by the delta-sigma modulator MOD and expands the extracted signal band components to a desired bit width. Further, the decimation filter FLT down-samples the expanded signal band components at a low data rate, and outputs the results of the down sampling as an A/D conversion result. The A/D conversion result is outputted as digital codes corresponding to the magnitude of the input analog signal Vin. In the example illustrated in FIG. 6, a 16-bit digital output D2 is outputted as the A/D conversion result of the A/D converter.
FIG. 7 is a view illustrating an example of signal paths for realizing a delta-sigma modulator provided in a delta-sigma A/D converter (see Non-Patent Document 3: FIG. 1, and Non-Patent Document 4: FIG. 1). In the delta-sigma modulator, there are various variations in the bit width of the output code, the order of the noise transfer function, the structure of signal paths, and the like, but, here, signal paths for realizing a 1-bit second-order delta-sigma modulator are illustrated as an example. In FIG. 7, each of reference characters AD1, AD2, AD3 and AD4 denotes an adder which adds two inputted signals and outputs the added result. In FIG. 7, the adder, to which a “−” (minus sign) is attached, means an adder which adds an input after reversing the sign of the input. Further, each of reference characters DL1, DL2, DL3 and DL4 denotes a delay device which delays an inputted signal by one cycle and outputs the delayed signal. Reference character AM1 denotes an amplifier which doubles an inputted signal and outputs the doubled signal, and reference character Q1 denotes a quantizer which quantizes an inputted signal. In many cases, the delta-sigma modulator is configured by a switched capacitor circuit, or the like, and performs arithmetic operation at discrete times, and hence, here, the time relation between the cycles is illustrated by using the delay devices.
In FIG. 7, the adder AD1 subtracts an output delta-sigma modulated signal V from an input analog signal U, and outputs the subtracted result as a signal S3. The adder AD2 adds the signal S3 to an output of the adder AD2 itself, which output is delayed for one cycle by the delay device DL1, and the adder AD2 outputs the added results as a signal S4. That is, the pair of the adder AD2 and the delay device DL1 functions as an integrator which integrates the signal S3 over time. The adder AD3 subtracts a signal S7 (doubled output delta-sigma modulated signal V) outputted from the amplifier AM1 from a signal S1 that is an output of the adder AD2, which output is delayed for one cycle by the delay device DL2, and the adder AD3 outputs the subtracted result as a signal S5. The adder AD4 adds the signal S5 to an output of the adder AD4 itself, which output is delayed for one cycle by the delay device DL3, and the adder AD4 outputs the added results as a signal S6. That is, the pair of the adder AD4 and the delay device DL3 functions as an integrator which integrates the signal S5 over time. The quantizer Q1 quantizes a signal S2 that is an output of the adder AD4, which output is delayed for one cycle by the delay device DL4, and the quantizer Q1 outputs the output delta-sigma modulated signal V of “1” or “−1”. The quantizer Q1 outputs “1” in the case where the inputted signal S2>0, and outputs “−1” in the case where the inputted signal S2<0. That is, the output delta-sigma modulated signal V, which is the output of the quantizer Q1, is a binary (1 bit) signal.
In the delta-sigma modulator having the signal paths illustrated in FIG. 7, the output delta-sigma modulated signal V is negative-fed back through the adders AD1 and AD3 in a duplicated manner. For this reason, when the signal S2 is increased, the output delta-sigma modulated signal V becomes “1”, so that the signal S7 becomes “2”. Thereby, the adder AD3 operates to reduce the signals S5 and S6, so that the signal S2 is reduced. Further, when the signal S1 is increased, the adder AD3 operates to increase the signals S5, S6 and S2, so that the output delta-sigma modulated signal V becomes “1”. When the output delta-sigma modulated signal V becomes “1”, the adder AD1 operates to reduce the signal S3, and also the adder AD3 operates to reduce the signal S5. As a result, the signals S1 and S2 are reduced. It is known that, with such negative feedback, the divergence does not occur in the signal paths illustrated in FIG. 7 in the region in which the input analog signal U is not excessive. For example, by the use of the arithmetic operation circuit having the signal paths as illustrated in FIG. 7, the delta-sigma modulator MOD illustrated in FIG. 6 can be realized.
FIG. 8 is a view in which the signal paths of the 1-bit second-order delta-sigma modulator illustrated in FIG. 7 is illustrated by using z operators. In FIG. 8, reference characters AD1 and AD2 respectively denote adders, and reference characters INT1 and INT2 respectively denote integrators. Reference character AM1 denotes an amplifier in which the inputted signal is amplified to be doubled, and reference character Q1 denotes a quantizer which quantizes the inputted signal. Reference character U1 denotes an arithmetic operation block configured by the adder AD1 and the integrator INT1. As illustrated in FIG. 8, the arithmetic operation unit configured by the adder AD2 and the delay devices DL1 and DL2 in FIG. 7 can be expressed as the integrator INT1, and the arithmetic operation unit configured by the adder AD4 and the delay devices DL3 and DL4 in FIG. 7 can be expressed as the integrator INT2. Further, the quantizer Q1 binarizes the inputted signal by determining the magnitude of the inputted signal, but this arithmetic operation performed by the quantizer Q1 can be modeled by adding quantization noise to the inputted signal. Accordingly, in FIG. 8, the quantizer Q1 is illustrated as a block which outputs a signal formed by adding quantization noise E to the signal S2.
When the signal paths illustrated in FIG. 7 are expressed and arranged by using the z operator as illustrated in FIG. 8, a noise transfer function NTF (z) from the quantization noise E to the output V, and a signal transfer function STF (z) from the input U to the output V are expressed as follows.NTF(z)=(1−z−1)2 STF(z)=z−2 These expressions indicate that the input U appears in the output V as it is, and that the quantization noise E is diffused into the high frequency range and outputted. In the delta-sigma A/D converter, a decimation filter is provided in the subsequent stage of the delta-sigma modulator as described above, and thereby an A/D conversion result is obtained by eliminating the quantization noise diffused into the high frequency range.
Next, there will be described a circuit configuration in which the signal paths for realizing the delta-sigma modulator described above are formed on a semiconductor integrated circuit. Each of FIG. 9A and FIG. 9B is a view illustrating an example of an arithmetic operation (addition and integration) circuit having a single-end structure (see Patent Document 1: FIG. 1, Patent Document 3: FIG. 3 and FIG. 6, Patent Document 4: FIG. 6). An example of the circuit configuration which realizes the functions of the arithmetic operation block illustrated in FIG. 9A is illustrated in FIG. 9B. That is, as illustrated in FIG. 9A, the arithmetic operation circuit illustrated in FIG. 9B realizes an arithmetic operation block configured by an adder ADD which adds input signals (input voltages) V1 and V2, and an integrator INT which integrates the addition result from the adder ADD and outputs the integration result as an output signal (output voltage) Vout.
In FIG. 9B, reference characters C1 and C2 respectively denote sampling capacitors, and reference character C3 denotes an integration capacitor. Reference character OPA denotes an operational amplifier. Reference characters SW1, SW2, SW3, SW4, SW5 and SW6 respectively denotes switches. Conduction/non-conduction (on/off) of each of the switches SW1, SW3 and SW5 is controlled by a signal φ1. Conduction/non-conduction (on/off) of each of the switches SW2, SW4 and SW6 is controlled by a signal φ2. The capacitors C1, C2 and C3 are assumed to have the capacitance values C1, C2 and C3, respectively. In the capacitors C1 and C2, the left side node (electrode on the side of the switches SW1 and SW3) is referred to as a bottom plate, and the right side node (electrode on the side of the switch SW6) is referred to as a top plate.
In the circuit illustrated in FIG. 9B, the signals φ1 and φ2 are controlled on the basis of a clock signal, or the like, and the addition of the input signals V1 and V2, and the integration of the addition result are performed by alternately turning on either the group of the switches SW1, SW3 and SW5, or the group of switches SW2, SW4 and SW6.
First, when the switches SW1, SW3 and SW5 are turned on by the signal φ1, and when the switches SW2, SW4 and SW6 are turned off by the signal φ2, the voltage V1 is applied to the bottom plate of the capacitor C1, and the voltage V2 is applied to the bottom plate of the capacitor C2. The top plates of the capacitors C1 and C2 are connected to 0 (V). The electric charges Q1 and Q2 which are respectively stored in the capacitors C1 and C2 at this time are expressed as follows.Q1=−C1·V1Q2=−C2·V2Thereby, the electric charges corresponding to the input voltages V1 and V2 are sampled by the capacitors C1 and C2, respectively. Further, when the voltage value of the output voltage Vout at this time is assumed to be Vout1, the electric charges Q3 stored in the capacitor C3 is expressed as follows.Q3=−C3−Vout1
Next, when the switches SW1, SW3 and SW5 are turned off by the signal φ1, and when the switches SW2, SW4 and SW6 are turned on by the signal φ2, the bottom plates of the capacitors C1 and C2 are connected to 0 (V), and the top plates of the capacitors C1 and C2 are connected to the negative side input terminal of the operational amplifier OPA. As a result, the circuit operates so that the electric charges stored in the capacitors C1 and C2 are transferred to the capacitor C3 by the operation of the operational amplifier OPA, and thereby the voltage value of the output voltage Vout is changed from Vout1 to Vout2. At this time, the charge conservation law is established as follows.−C3·Vout2=Q1+Q2+Q3Therefore, the voltage value Vout2 is expressed as follows.Vout2=Vout1+(C1/C3)V1+(C2/C3)V2That is, by a series of the operations, the voltage obtained by adding the (C1/C3) V1 and (C2/C3) V2 to the Vout1 is outputted as the output voltage Vout. Thereafter, the above-described operations are repeatedly performed in such a manner that the switches SW1, SW3 and SW5 are turned on by the signal φ1, and that the switches SW2, SW4 and SW6 are turned off by the signal φ2. Thereby, the arithmetic operation for adding the input signals V1 and V2, and for integrating the addition result is realized.
The above-described operation is expressed by the z operators as follows.Vout(z)=[(C1/C3)V1(z)+(C2/C3)V2(z)]/(z−1)In the arithmetic operation circuit illustrated in FIG. 9B, the arithmetic operation is performed in such a manner that the input signal (input voltage) V1 is scaled by (C1/C3) times, and that the input signal (input voltage) V2 is scaled by (C2/C3) times. The ratios of (C1/C3) and (C2/C3) are suitably changed according to the purpose of preventing the saturation of the signals in the circuit, the convenience of the design of the signal paths, and the like.
FIG. 10 is a view illustrating a circuit configuration of the input portion of the operational amplifier (see Non-Patent Document 5: FIG. 2). In FIG. 10, reference characters N1, M2 and M3 denote N-type MOS transistors, respectively. The MOS transistor M1 has a role of biasing the MOS transistors M2 and M3. The MOS transistors M2 and M3 form a pair of transistors whose source are connected to each other. The gate of the MOS transistor M2 corresponds to the positive side input node (positive side input terminal) IM of the operational amplifier, and the gate of the MOS transistor M3 corresponds to the negative side input node (negative side input terminal) IP of the operational amplifier.
The differential pair illustrated in FIG. 10 is normally operated, when the gate-source voltage of each of the MOS transistors M2 and M3 is lager than a voltage obtained by adding an overdrive voltage Vov of about 0.2 (V) to the threshold voltage Vth of the transistor. For example, when the threshold voltage of the transistor is assumed to be 0.6 (V), each of the MOS transistors M2 and M3 may be biased so that the gate-source voltage becomes 0.8 (V) (=0.2 (V)+0.6 (V)) or more. In order to enable the circuit to normally operate, the drain-source voltage of the MOS transistor M1 may be set to, for example, 0.2 (V) or more.
Because of the restrictions to enable each of the MOS transistors to normally operate, a potential of 1.0 (V) (=0.2 (V)+0.8 (V)) or more may be applied to each of the input terminals IM and IP in order to enable the operational amplifiers to normally operate. For example, when the power supply voltage is 3.0 (V), the operational amplifier does not operate as expected unless the potential of each of the input terminals IM and IP is in the range of 1.0 (V) to 3.0 (V). In this way, the operational amplifier does not operate unless the potential of each of the input terminals IM and IP is actually set at a high potential to some extent. For this reason, even in the operational amplifier included in the delta-sigma A/D converter, the voltage applied to the input terminal of the operational amplifier may be in the suitable range. The voltage range of the input terminal of the operational amplifier, which voltage range is suitable for the normal operation of the operational amplifier, is referred to as a common mode input voltage range.
The arithmetic operation circuit illustrated in FIG. 9B has a single-end structure. However, in an actual semiconductor integrated circuit, the arithmetic operation circuit is formed in a differential structure in many cases because of such advantages as that, as compared with the single-end structure, the differential structure can be used for a signal having large amplitude and is hardly influenced by common mode noise. In the following, there will be described examples of an arithmetic operation circuit having a differential structure and used in a delta-sigma A/D converter.
FIG. 11 is a view illustrating an example of a circuit configuration of a switched capacitor integrator having a differential structure (see Patent Document 2: FIG. 7, Patent Document 6: FIG. 7). In FIG. 11, reference characters C1P and C1M respectively denote sampling capacitors, and reference characters C2P and C2M respectively denote integration capacitors. Reference character OPA denotes a fully differential operational amplifier. Reference characters SW1, SW2, SW3, SW4, SW5, SW6, SW7 and SW8 respectively denote switches. Conduction/non-conduction (on/off) of each of the switches SW1, SW2, SW5 and SW6 is controlled by a signal φ1. Conduction/non-conduction (on/off) of each of the switches SW3, SW4, SW7 and SW8 is controlled by a signal φ2. Reference character VIP denotes a positive side input node and reference character VIM denotes a negative side input node. Reference character VOP denotes a positive side output node, and reference character VOM denotes a negative side output node. Note that, in the following, the name of a signal inputted or outputted to or from each node, and the voltage value of the each node are also suitably represented by using the same reference character as the reference character given to the node. Reference character SG denotes a signal source which outputs a differential input signal (VIP−VIM). The signal source SG is provided outside a semiconductor integrated circuit (IC) in which the switched capacitor integrator having the differential structure is formed.
The arithmetic operation circuit (switched capacitor integrator) illustrated in FIG. 11 has functions of integrating the differential input signal (VIP−VIM) supplied from the signal source SG, and of outputting the integration result as a differential output signal (VOP−VOM). In the arithmetic operation circuit illustrated in FIG. 11, the operational amplifier OPA performs the common mode feedback by referring to a common mode potential VCM so that the common potential of the output signals VOP and VOM becomes VCM, that is, is expressed as (VOP+VOM)/2=VCM. Note that, in FIG. 11, the common mode potential VCM is assumed to be an intermediate potential between a power supply voltage VDD and a ground voltage VSS (0 (V)). Reference character VICM denotes an intermediate potential between the input signals VIP and VIM, that is, a common mode potential of the input signal. The capacitance values of C1P and C1M are set to be the same capacitance value of C1, and the capacitance values of C2P and C2M are set to be the same capacitance value of C2.
In the arithmetic operation circuit illustrated in FIG. 11, first, when the switches SW1, SW2, SW5 and SW6 are turned on by the signal φ1, and when the switches SW3, SW4, SW7 and SW8 are turned off by the signal φ2, the voltages VIP and VIM are applied to the bottom plates of the capacitors C1P and C1M, respectively. The top plates of the capacitors C1P and C1M are connected to the common mode potential VCM. The charges Q1P and Q1M respectively stored in the capacitors C1P and C1M at this time are expressed as follows.Q1P=(VCM−VIP)C1Q1M=(VCM−VIM)C1The charge corresponding to the difference between the common mode potential VCM and the input voltage VIP is sampled by the capacitor C1P. The charge corresponding to the difference between the common mode potential VCM and the input voltage VIM is sampled by the capacitor C1M. Further, at this time, when it is assumed that the voltage value of the output signal VOP is VOP1, and that the voltage value of the output signal VOM is VOM1, the sum of the charges stored in the capacitors C2P and C2M is expressed as follows.(VOP1−VCM)C2+(VCM−VOM1)C2=(VOP1−VOM1)C2
Next, when the switches SW1, SW2, SW5 and SW6 are turned off by the signal φ1, and when the switches SW3, SW4, SW7 and SW8 are turn on by signal φ2, the bottom plates of the capacitors C1P and C1M are connected to the common mode potential VCM. The top plate of the capacitor C1P is connected to the negative side input terminal of the operational amplifier OPA, and the top plate of the capacitor C1M is connected to the positive side input terminal of the operational amplifier OPA. As a result, by the operation of the operational amplifier OPA, the voltage value of the output signal VOP is changed to VOP2, and the voltage value of the output signal VOM is changed to VOM2. At this time, when the charges in the previous state are assumed to be conserved, the following expression is established.(VOP2−VOM2)C2=(VOP1−VOM1)C2+Q1P−Q1M Therefore, the following expression is established.(VOP2−VOM2)=(VOP1−VOM1)+(VIP−VIM)C1/C2That is, the differential output voltage expressed as (VOP2−VOM2) becomes the sum of the differential output voltage of one previous operation, which voltage is expressed as (VOP1−VOM1), and the product of the differential input voltage with the capacitance ratio, which product is expressed as (VIP−VIM) (C1/C2). This is corresponds to one integration operation.
Here, the common mode potential VCM of the differential signal in the semiconductor integrated circuit is a potential determined according to the power supply voltage of the semiconductor integrated circuit. The common mode potential VICM of the input signal is a potential determined according to the signal source SG outside the semiconductor integrated circuit. Therefore, the common mode potential VCM and the common mode potential VICM are not directly related to each other. Generally, in a differential input A/D converter, two input terminals for inputting the differential input signals (VIP and VIM) are provided, but the input terminal for inputting the common mode potential VICM of the input signal is not provided. It is preferred that the arithmetic operation of a differential signal is normally performed by the circuit regardless of the relationship between the common mode potential VCM and the common mode potential VICM of the input signal.
However, in the arithmetic operation circuit illustrated in FIG. 11, when the common mode potential VCM and the common mode potential VICM of the input signal are significantly different from each other, there arises a problem that the potential of the node VA deviates from the suitable input voltage range of the operational amplifier OPA, so as to prevent the operation of the integrator. This is because the potential of the node VA is determined by the charges sampled in the capacitors C1P and C1M during the φ1-period and by the capacitive division circuit configured by the operation of the switches during the φ2-period. Note that the φ1-period is the period in which the switches controlled by the signal φ1 is turned on, that is, the period in which the switches SW1, SW2, SW5 and SW6 are turned on, and in which the switches SW3, SW4, SW7 and SW8 are turned off. Further, the φ2-period is the period in which the switches controlled by the signal φ2 is turned on, that is, the period in which the switches SW1, SW2, SW5 and SW6 are turned off, and in which the switches SW3, SW4, SW7 and SW8 are turned on.
In the arithmetic operation circuit illustrated in FIG. 11, the amount of charges sampled by the capacitors C1P and C1M in the φ1-period is held as it is during the φ2-period, and hence the following expression is established.(VCM−VIP)C1+(VCM−VIM)C1=2(VA−VCM)C1The above expression is rearranged with VA, so that the following expression is obtained.VA=2VCM−(VIP+VIM)/2=2VCM−VICM That is, the potential of the input node VA of the operational amplifier OPA is converged to the potential obtained by subtracting VICM from 2VCM. For example, when the common mode potential VCM is 1.5 (V), and when the common mode potential VICM of the input signal is 2.5 (V), the potential of the input node VA of the operational amplifier OPA is converged to 0.5 (V). However, as described above, there is a restriction in the range of the common mode input voltage of the operational amplifier OPA. For example, when the potential of the input nodes IM and IP of the operational amplifier is 0.5 (V) in the circuit illustrated in FIG. 10, the differential pair is cut off, so that the desired operation is not performed. When the circuit configuration in the operational amplifier OPA of the arithmetic operation circuit illustrated in FIG. 11 is assumed to be the same as the circuit configuration illustrated in FIG. 10, the common mode potential VICM of the input signal is set in a voltage range of 0 (V)<VICM<2.0 (V) in order to enable the operational amplifier OPA to normally operate.
The existence of this restriction becomes a problem in particular when a single end signal is A/D converted by using a differential input A/D converter. For example, when a single end signal is A/D converted by a differential input A/D converter, one side of the two input terminals is set to a fixed potential. However, in the A/D converter using the arithmetic operation circuit illustrated in FIG. 11, for example, in the case where the negative side input terminal VIM is set to 1.5 (V), and where the positive side input terminal VIP is connected to the signal source, when a signal of 2.5 (V) or more is applied from the signal source, the common mode potential VICM of the input signal becomes larger than 2.0 (V), so as to prevent the operation of the circuit. In this way, in the case where the arithmetic operation circuit illustrated in FIG. 11 is used for a delta-sigma A/D converter, there is a problem that the user's design of the signal source is greatly restricted.
As a circuit configuration which eliminates the above-described problem in the arithmetic operation circuit illustrated in FIG. 11, an arithmetic operation circuit illustrated in FIG. 12 is proposed (see Patent Document 7: FIG. 4). FIG. 12 is a view illustrating another example of a circuit configuration of a switched capacitor integrator having a differential structure. In FIG. 12, components having the same functions as the functions of the components illustrated in FIG. 11 are denoted by the same reference characters, and the duplicated explanation thereof is omitted. The arithmetic operation circuit illustrated in FIG. 12 is provided with capacitive elements C3P and C3M which are not provided in the arithmetic operation circuit illustrated in FIG. 11. Each of the capacitive elements C3P and C3M may be formed by parasitic capacitance and hence is illustrated by a broken line. Further, the arithmetic operation circuit illustrated in FIG. 11 is configured such that the bottom plate of the capacitor C1P can be connected to the common mode potential VCM via the switch SW3, and such that the bottom plate of the capacitor C1M can be connected to the common mode potential VCM via the switch SW4. On the other hand, in the arithmetic operation circuit illustrated in FIG. 12, the bottom plates of the capacitors C1P and C1M are configured to be mutually connectable via the switch SW3.
In the arithmetic operation circuit illustrated in FIG. 12, in the φ1-period, the bottom plates of the capacitive elements C3P and C3M are connected to 0 (V), and the top plates of the capacitive elements C3P and C3M are connected to the common mode potential VCM. The voltages VIP and VIM are respectively applied to the bottom plates of the capacitors C1P and C1M, and the top plates of the capacitors C1P and C1M are connected to the common mode potential VCM. Thereby, the capacitive elements C3P and C3M are respectively charged to the common mode potential VCM, and the charge corresponding to the difference between the common mode potential VCM and each of the input voltages VIP and VIM is sampled by each of the capacitors C1P and C1M.
Next, when the period φ1 is shifted to the period φ2, so that the switches SW3, SW7 and SW8 are turned on, the potential of the input node VA of the operational amplifier OPA is made to converge to the common mode potential VCM to which the capacitors C3P and C3M are charged beforehand. Actually, the potential of the input node VA of the operational amplifier OPA may be different from the common mode potential VCM at first, due to the parasitic capacitance, and the like, of the operational amplifier OPA, and of the capacitors C2P and C2M, but is made to converge to the common mode potential VCM after repetition of several cycles of the above operation. In this way, when a switched capacitor integrator having a differential structure is configured as illustrated in FIG. 12, a differential input signal of any common mode potential can be inputted into the switched capacitor integrator.
The arithmetic operation circuit illustrated in FIG. 12 is a simple integrator, but a delta-sigma modulator is provided with an arithmetic operation (1-bit DAC and addition and integration) circuit, such as the arithmetic operation block U1 illustrated in FIG. 8, which integrates a value obtained by adding a binary reference voltage to an input voltage. FIG. 13 is a view illustrating an example of an arithmetic operation (1-bit DAC and addition and integration) circuit having a differential structure. In FIG. 13, reference characters C3P and C3M respectively denote reference capacitors. Reference characters SW9, SW10, SW11, SW12, SW13 and SW14 respectively denote switches. Reference character Vref denotes a reference voltage. The other components are the same as the components denoted by the same reference characters in FIG. 12, and hence the duplicated explanation thereof is omitted.
The conduction/non-conduction (on/off) of each of the switches SW9 and SW12 is controlled by the signal φ1. Conduction/non-conduction (on/off) of each of the switches SW10, SW11, SW13 and SW14 is controlled by the signal φ2 and a signal y (or an inverted signal yx of the signal y). When the signal φ2 is “1” and the signal y is “+1”, the switches SW10 and SW14 are made conductive (turned on), and in the other cases, the switches SW10 and SW14 are made non-conductive (turned off). When the signal φ2 is “1” and the signal y is “−1”, the switches SW11 and SW13 are made conductive (turned on), and in the other cases, the switches SW11 and SW13 are made non-conductive (turned off). Here, signal y corresponds to the feedback signal of the delta-sigma modulator, and has a 1 bit (binary) value as described above. Further, the capacitance values of the capacitors C3P and C3M are assumed to be the same.    [Patent Document 1] Japanese Laid-Open Patent Publication No. 08-125541    [Patent Document 2] Japanese Laid-Open Patent Publication No. 2002-261614    [Patent Document 3] Japanese Laid-Open Patent Publication No. 2001-358591    [Patent Document 4] U.S. Pat. No. 4,851,841    [Patent Document 5] U.S. Pat. No. 4,939,516    [Patent Document 6] U.S. Pat. No. 4,972,436    [Patent Document 7] U.S. Pat. No. 6,768,436    [Patent Document 8] Japanese Laid-Open Patent Publication No. 2007-300225    [Patent Document 9] Japanese Laid-Open Patent Publication No. 2006-41992    [Patent Document 10] Japanese National Publication of International Patent Application No. 10-508167    [Non-patent Document 1] Akira Yukawa, “Oversampling A-D conversion technology,” Nikkei BP Company, 1990    [Non-patent Document 2] Richard Schreier and Gabor C. Temes (original authors), Takao Waho, Akira Yasuda (translation supervisors), “Introduction to Delta-Sigma Type Analog/Digital Converter,” Maruzen, 2007    [Non-patent Document 3] B. E. Boser and B. A. Wooley, “The design of sigma-delta modulation analog-to-digital converters,” IEEE Journal of Solid-State Circuits, Vol. 23, pp. 1298-1308, December 1988.    [Non-patent Document 4] B. P. Brandt, D. E. Wingard, and B. A. Wooley, “Second-order sigma-delta modulation for digital-audio signal acquisition,” IEEE journal of Solid-State Circuits, Vol. 26, pp. 618-627, April 1991.    [Non-patent Document 5] M. W. Hauser, P. J. Hurst, and R. W. Brodersen, “MOS ADC-Filter Combination That Does Not Require Precision Analog Components,” IEEE International Solid-State Circuits Conference 1985 Digest of Technical Papers, pp. 80-82, 1985.
The arithmetic operation circuit illustrated in FIG. 13, which is a diagram referred to in conceiving the embodiments, subtracts the signal y from the differential input signal and integrates the subtraction result, so as to output the integration result. Actually, the charge expressed by a product of the reference voltage Vref with each of the capacitance value of the reference capacitors C3P and C3M corresponds to the signal y.
In the arithmetic operation circuit illustrated in FIG. 13, in the φ1-period, the voltages VIP and VIM are respectively applied to the bottom plates of the capacitors C1P and C1M, and the top plates of the capacitors C1P and C1M are connected to the common mode potential VCM, so that the sampling of the differential input signal is performed. At this time, both the electrodes (the bottom plate and the top plate) of each of the capacitive elements C3P and C3M are connected to the common mode potential VCM, and hence the charge of the capacitive elements C3P and C3M becomes zero.
Next, when the φ1-period is shifted to the φ2-period, the switches SW3, SW7 and SW8 are turned on, and the charge stored in each of the capacitors C1P and C1M by the sampling is transferred to each of the capacitors C2P and C2M. Further, in the φ2-period, when the value of the signal y is “+1”, the switches SW10 and SW14 are turned on. Thereby, the bottom plate of the capacitor C3P is connected to the reference voltage Vref, and the bottom plate of the capacitor C3M is connected to 0 (V). On the contrary, when the value of the signal y is “−1”, the switches SW11 and SW13 are turned on. Thereby, the bottom plate of the capacitor C3P is connected to 0 (V), and the bottom plate of the capacitor C3M is connected to the reference voltage Vref. As a result, a value obtained by subtracting a signal corresponding to the reference voltage from each of the sampled input signals, or a value obtained by adding a signal corresponding to the reference voltage to each of the sampled input signals is integrated.
In the case where a delta-sigma modulator provided in a delta-sigma A/D converter is configured by using the arithmetic operation circuit illustrated in FIG. 13, there is a problem that the settable range of the reference voltage Vref is narrow. The reference voltage Vref defines the full scale range of A/D conversion in the delta-sigma A/D converter, and hence it is desirable that a user can arbitrarily set the reference voltage Vref. In the arithmetic operation circuit illustrated in FIG. 13, the charge of each of the capacitors C3P and C3M is discharged to zero in the φ1-period. In the next φ2-period, the respective switches are controlled so that the potential difference between the reference voltage Vref and 0 (V) is divided by the capacitance ratio of the capacitors C3P and C3M, and thereby the potential of the input node VA of the operational amplifier OPA becomes a voltage divided by the capacitance ratio of the capacitors C3P and C3M. That is, the potential of the input node VA is set to VA=Vref/2.
For this reason, when a low reference voltage Vref, which causes the potential (Vref/2) of the input node VA to become lower than the common mode input voltage range of the operational amplifier OPA, is used, the circuit does not operate. For example, when the power supply voltage VDD is 3.0 (V), and also the ground voltage VSS is 0 (V), and when the common mode potential VCM is 1.5 (V), and also the reference voltage Vref is 1.0 (V), the potential of the input node VA is made to converge to VA=Vref/2=0.5 (V). However, when the configuration in the operational amplifier OPA of the arithmetic operation circuit illustrated in FIG. 13 is the same as the configuration illustrated in FIG. 10, the differential pair is cut off, so that a desired operation is not performed. In order to normally operate the circuit, the reference voltage Vref may be set as Vref>2.0 (V). In such case, for example, the voltage of 1.2 (V) generated in the band gap reference circuit is not used as the reference voltage Vref of the arithmetic operation circuit illustrated in FIG. 13. In order to increase the flexibility of design for a user of a semiconductor integrated circuit, it is preferred that the settable voltage range of the reference voltage Vref is as wide as possible.